There are some parameters we need to follow in order to use the table 4A. For example, for panelboards or other equipment rated 240V and below, if I have a fault current at 3kA or less, and the fault clearing time is more than 0.03s, can I still use that table? You can have this kind of case in a lot of downstream system which is far away from the transformer.

Per the standard, yes you can use the table. However, if you calculate the energy level using IEEE 1584, you may the energy to be quite high Especially if it is on the secondary side of a transformer with no other protective device between the transformer secondary and the panelboard. That is because the primary device must sense the fault and trip. The primary device thinks it is an overload condition and make take 5 or more seconds to operate. That is a long time when a arc flash is occuring.

No, you can't use the table. All the entries for a 240 V panelboard require a maximum fault current of 25 kA and a maximum fault clearing time of 0.03 seconds or less. The only section that might be considered is 600 V switchgear with a maximum 0.5 second clearing time, but the construction of switchgear is very different from a panelboard so this isn't really valid.

Going by IEEE 1584 in the current edition, if you are under 240 V (208 V or less) and the transformer is 125 kVA or less, then it would be considered <1.2 cal/cm^2. More recent research has shown that this boundary is not sufficient but at this time we do not have updated guidance from a newer version of the IEEE 1584 standard. If you don't do this, then you will have to use either the Doan/Neal calculation of the IEEE 1584 calculation.

to meet 25 kA or less fault current is not very difficult, however, to meet maximum fault clearing time of 0.03 s is to be discussed. When you do your fault current calculation, it is based on the worst case scenario. A lot of impedance was ignore in your electrical circuits. So the fact is that the clearing time would be easily exceed 0.03s for the most of the cases. From my point of view, almost no chance to use table 4A at all. Any inputs?

I would recommend that you have a study done at your facility. This will define what the AFH is, what the proper PPE needed is, what the available short ckt is (over-dutied eqpt), what the coordination/selectivity is and recommendations to reduce AFH and improve coordination.

We actually seldom use that table 4A since I don't feel comfortable to meet those parameters set in each section. I just want to know if anyone use that before. Why does CSA Z462 adopt those tables if they are not useful?

The tables are fairly useful for some lighting panels. As long as your instantaneous trip point on the main breaker is sufficiently low that it will trip during an arcing fault or even better you have fuse protection, most smaller breakers such as residential or some commercial systems will easily meet the 30 ms (2 cycle) trip time from an instantaneous trip.

Thanks for the response! However, I still don't think it is safe to follow this for any arc flash analysis. We all know that the lower current will not result in a small incident energy since another big factor is the clearing time. So when we get the result for the detailed anlaysis or follow table 4A, it will not be the worse case scenario since the lower current will always presented in all different scenarios, and is not simply based on under utility or generator modes. I think that IEEE may even need to re-consider this again. Please be advised that the impedenance will be changed durning the any circumstances.

Feel free to provide your further comments!

If you take that approach then electrical work cannot be done safely under any circumstance. We have a standard for this. Power system analysis is fairly accurate and the types of faults are limited. IEEE ran hundreds of tests on arcing faults and include the raw data with IEEE 1584. Then they did curve fits and published this including a detailed analysis in the standard. The arcing current shows a bimodal distribution which is why you run the calculation twice at two different currents. In some circumstances one incident energy is larger than the other but if you are already below the instantaneous trip point of the ocpd, you will get a larger valur with the 85% value. IEEE then went on to test their calculation against the actual test data and showed that numerically when combined with similar estimates built into the ASTM test for atpv, the overall model works 95% of the time. A paper published by Doan in 2009 detailing 33 people exposed to arc flash showed that in all cases where the proper ppe was worn in the proper manner as determined using the ieee 1584 calculation, they walked away unharmed. So I completely disagree with the statement that you can't trust any of the calculations anyways because field "testing" and lab testing/modelling appear to agree. Where we get into a grey area with the tables is two items. First, some of the tables include provisions for reduced ppe for certain tasks. This is invalid. The Doan paper documented 3 cases where this was followed and resulted in burns. The problem is that the consequence is not being reduced, only the likelihood. So either ppe is requjred or it is not. Reduced ppe makes no sense at all and is no different than no ppe. The second issue is that in some cases in some versions of the table, the incident energy values are different from ieee 1584. I am not sure what the source of the erroneous values was. in the table, the assumption is missing one critical factor. You have to check the trip time at 85% of the bolted fault current. In addition one glaring issue with the tables is that the end user would most likely use a simple method of calculating bolted fault current such as assuming zero impedance in cables and an infinite source on the primary of the transformer and zero inductance so that only transformer % Z matters and is modeled as purely resistive. This is a very common assumption for sizing AIC but totally invalid for arc flash and results in low values. The alternative detailed model essentially results in doing an arc flash analysis as per 1584 anyways.The result is that the only time that the tables are useful is when an arc flash analysis has not been done and so they are better than nothing such as when doing the first gathering of data on an existing facikity where doors have to be opened with no knkwledge of what is behind them.

Great! I think that I have been convinced! Thanks!

In table 4A and 4B parameters, the maximum of up to certain cycle fault clearing time is based on short circuit current or arc fault current?

Short circuit current.

To put this in perspective and close out some of the side commnets...

The theory behind the Lee equation is that the load is mostly inductive and the arc is mostly resistive. So if we look at maximum power transfer to the arc then 50% of the power is in the arc and 50% is in the load/cabling. At that point, the current will be half of the bolted fault current. So knowing that power is approximately equal to V*I and knowing the bolted fault current, the arcing power is at least proportional to V*I*0.5. The arcing energy is then V*I*0.5*time. Then if we know distance from the arc and assuming that the radiant heat is a perfect point source, the incident energy is proportional to the arc power divided by the square of the distance (area of a sphere).

There are a number of issues with the Lee approach and there is no value in arguing over the finer details of arc physics here. I'm using it is a grossly simplified way to getting to answering the question. Suffice to say that the current IEEE 1584 empirical method has about the same form as Lee but has some exponents and some additional correction factors.

So...getting back to the original issue. So if I have a fixed maximum voltage (say 240 V), current, time, and distance, then lowering any of these values will result in a lower incident energy. If one or more of these values is higher than those maximums, then clearly I at least might have a higher incident energy. The critical one is time. Typically if I lower the arcing current, the time for the overcurrent protective device to open grows at a much faster rate (it's not linear), resulting in values higher than those projected in the table. But if all of the values are equal to or less than the parameters in the table then by extension, the incident energy will be less.

The reality though is that there are a variety of methods (both IEC and ANSI) of estimating short circuit current which are fine for equipment sizing purposes because they are conservative. In fact they are so simple to use that I can do them with a calculator and a napkin. However applying those conservative values to trip curves then results in an underestimated trip time (trips faster than expected). And that's the fundamental issue with trying to use the tables. By the time you actually do the detailed analysis to determine short circuit current accurately enough to get to a valid trip time, the effort to calculate arc flash incident energy using IEEE 1584, even by hand, is trivially simple.

I suggest using instead estimates that are not based on time limitations for low voltages. IEEE 1584 contains the "240 V rule", even if there is controversy about the right transformer size. NESC contains a similar rule (actually a table) that works for any size transformer as long as the voltage is below a threshold which is based on tests that were done. The NESC rule in particular is easy to implement because it gives a value of 4 cal/cm^2 for all conditions below 300 V nominal. IEEE 1584 rule is "single transformer less than 125 kVA with nominal voltage under 240 V". Still, neither one depends on a lot of unknowns such as short circuit current or especially trip times.